This invention generally relates to a method and an apparatus for performing wafer to wafer bonding of different semiconductor materials and more specifically, relates to a method and an apparatus for smoothing the wafer surface to a roughness of less than 9 Angstroms root mean square (RMS) over a 20 microns dimensionality across the wafer. Preferably, this method provides for polishing of a wafer to achieve the desired smoothness while reserving the overall wafer flatness across the wafer to achieve a final smoothed surface which can be chemically cleaned using conventional cleaning procedures for performing wafer bonding.
Silicon-on-Insulator (SOI) is a current technology for fabricating semiconductor devices such as field effect transistors (FETs) using a thin layer of silicon separated dielectrically from a substrate by a layer of insulating material. Devices fabricated using SOI structures exhibit greatly reduced parasitic capacitance compared with devices simply fabricated on bulk silicon. For this reason, SOI technology has become a vital and critical part of IBM""s strategy to incorporate and implement into present manufacturing of CMOS technology and to become the OEM of high speed IC""s on insulator. However, this strategy does depend on a cost-effective and reliable supply of SOI substrates suitable for integration into mainstream CMOS manufacturing processing.
Most of the high quality SOI substrates which are currently commercially available are produced through ion implantation of a silicon wafer to create a buried insulating layer below the surface of the silicon wafer. An example of such a SOI structure is a substrate produced by the SIMOX (Separation by Implanted OXygen) process such as described in U.S. Pat. No. 5,930,643 by D. K. Sadana et al. which issued Jul. 27, 1999 or in U.S. Pat. No. 6,090,689 by D. K. Sadana which issued Jul. 18, 2000. The applications of these SOI structures are limited in that the surface layer must be the same material as the underlying Si wafer. Also, this surface silicon layer is damaged during the high energy implantation process and typically requires a high temperature (i.e. 1000-1300 C.) annealing process to remove the implant damage. Similarly, the insulating layer in this approach is limited in that only oxide compounds of silicon can be,formed by this technique and so, in practice, it is limited to forming either a silicon dioxide or silicon oxynitride buried layer. Subsequently, more complicated material structures or stacks containing layer materials other than these mentioned silicon oxides are not practical and in principle very difficult to fabricate. Furthermore, the thickness of the buried insulating layer is also limited and difficult to control using the SIMOX technique. For example, a very thin buried oxide (BOX) layer of 5 nm or a thick BOX of 1 micron is very difficult to achieve using the SIMOX approach.
Another method for fabricating SOI structures is by wafer bonding whereby two substrates are bonded together with silicon dioxide as the bonding layers. Moreover, in this approach the desired or required film or layer stack is initially deposited on the surfaces of the two separate wafers, i.e. seed and handle wafers and ultimately, these films will be used to form the buried insulating layer as well as the desired layer or layered structure for device fabrication. These two seed and handle wafers will be polished if required and then be directly bonded together using a top surface to a top surface orientation. One of the wafers, i.e. seed wafer, is then thinned down to create the SOI structure using an etch back technique or a wafer cleaning technique such as the Smart-CutÒ, SiGen or Eltran process. The Smart-CutÒ process is described in U.S. Pat. No. 5,374,564 by M. Bruel which issued Dec. 20, 1994.
In general, wafer bonding is a powerful and flexible technique for creating SOI films and other layered-stacked substrates suitable for device fabrication and yet, can still be amenable or applicable to a variety of integration schemes which provide some key advantages over ion implantation approaches. Typically, because this method involves the layer transfer of one or more films from a seed wafer to a handle substrate, there is a greater flexibility in the type and quality of the material stack that can be created or bonded to an buried insulator layer. Specifically, this method allows the transfer of semiconductor films other than silicon such as Inp, GaAs, etc. for potential mixed III-V to II-VI device integration schemes as well as other buried metal films such as W, Pt, etc. which are suitable for buried interconnects, dual gates or ground plane device applications. Understandable, such types of surface or buried structures incorporating these type of lattice-mismatched, metal or insulating layers can not be simply formed or created by the ion implant approach. Also, wafer bonding can be performed at low temperatures ranging from room temperature (23 C.) to 400 C. which will subsequently allow for multiple bonding steps to be performed on a single wafer if so desired without effecting the electrical properties of the existing devices or the integrated circuits. These advantages have made possible many new developments in the design and fabrication of novel semiconductor devices such as the Double-Gate Devices or back-plane device structures.
Smoothing or planarization of SiGe for epitaxial growth has been shown in U.S. Pat. No. 6,107,653 by E. A. Fitzgerald in an epitaxial growth application on bulk silicon. In U.S. Pat. No. 6,107,653, chemo-mechanical polishing (CMP) of the upper surface of a graded SiGe layer was performed to remove the roughness created by dislocations introduced during relaxation of the SiGe layer. The planarization of the surface was for the purpose of preventing the continued roughening and grooving of the surface that leads to dislocation blocking. Planarization prevented a rise in the threading dislocation density during subsequent growth of the graded SiGe layer. However, there is no mention of forming a bondable surface, wafer uniformity, or the roughness quantification in terms of RMS.
The key to the wafer bonding approach and its benefits is realistically based upon the ability to consistently perform and generate a high quality wafer to wafer bonding process. Critical prerequisites for performing good quality wafer bonding of two different substrates requires that the surfaces to be bonded to be extremely flat (i.e. less than 10 Angstroms) and to be completely free of any foreign particles or contaminants. Moreover, it is critical that the surface roughness be less than 9 angstroms root mean square (RMS) over a 20 microns square geometry in order to achieve a successful and high quality bonding interface between the two substrates. These restricted requirements prevent the bonding of most xe2x80x9cas-grownxe2x80x9d materials since their initial film topography after the growth processes is typically so much greater than the critical 9 angstroms value necessary for bonding. However, since it is possible to grow high quality thermal oxide layers with the necessary surface properties for bonding there are bonded SOI wafers which are created by directly bonding a bulk silicon wafer to a thermal oxide layer in order to form a BOX structure and are commercially available from SOITECH.
In accordance with the present invention, a method and an apparatus is provided/described for performing wafer to wafer bonding for many different materials by smoothing the wafer surface to a roughness of less than 9 angstroms root mean square (RMS) using a process of Chemical Mechanical Planarization (CMP).
This invention further provides a method and apparatus for performing wafer to wafer bonding for many materials by smoothing the wafer surface to a roughness of less than 9 Angstroms RMS over 20 microns. Moreover, smoothing of the entire wafer surface can be accomplished by the CMP process while preserving and maintaining the overall wafer flatness across the wafer. After the CMP process, the final surface can be effectively cleaned using a brush clean to remove particles and a conventional RCA or standard cleaning 1 and 2 (SCxe2x88x921,xe2x88x922) chemical cleaning procedure to prepare the wafer surfaces for wafer bonding. This invention has been used to smooth and successfully bond Low Temperature Oxide (LTO) layers, polysilicon layers, and silicon germanium (SiGe) layers thereby providing the capability to create and fabricate complex material stacks and devices. The ability to smooth and bond LTO films is particulary important and useful for fabricating semiconductor devices since LTO layers can be easily deposited at low temperatures over a variety of materials which initially may not be suitable for CMP polishing or be too rough for wafer bonding. Once deposited the initial roughness of the starting material will be translated over to the surface of the LTO layer which can then be readily smoothed to a high surface quality of 9 Angstroms RMS or less in roughness by this invention. It has been demonstrated that once the surface of the LTO layer is smoothed properly that the LTO layer can be use to perform strong, high quality wafer to wafer bonding to another wafer, ie. handle wafer. In this fashion, a LTO layer can be used as an intermediate buffer layer to provide the xe2x80x9cgluexe2x80x9d or xe2x80x9cadhesivesxe2x80x9d to enable the bonding of a wide range of materials and devices. As a result of this invention, wafer bonding has been incorporated as an important component of new SOI based devices, including double gate devices and SiGe-On-Insulator (SGOI) device structures.